1. Field of the Invention
This invention relates generally to the testing of digital signal processing units and, more particularly, to the signals that are transmitted from a target processor to a host processing unit to permit analysis of the target processor operation. Certain events in the target processor must be communicated to the host processing unit along with contextual information. In this manner, the test and debug data can be analyzed and problems in the operation of the target processor identified.
2. Description of the Related Art
As microprocessors and digital signal processors have become increasingly complex, advanced techniques have been developed to test these devices. Dedicated apparatus is available to implement the advanced techniques. Referring to FIG. 1, a general configuration for the test and debug of a target processor 12 is shown. The test and debug procedures operate under control of a host processing unit 10. The host processing unit 10 applies control signals to the emulation unit 11 and receives (test) data signals from the emulation unit 11 by cable connector 14. The emulation unit 11 applies control signals to and receives (test) signals from the target processing unit 12 by connector cable 15. The emulation unit 11 can be thought of as an interface unit between the host processing unit 10 and the target processor 12. The emulation unit 11 processes the control signals from the host processor unit 10 and applies these signals to the target processor 12 in such a manner that the target processor will respond with the appropriate test signals. The test signals from the target processor 12 can be a variety types. Two of the most popular test signal types are the JTAG (Joint Test Action Group) signals and trace signals. The JTAG protocol provides a standardized test procedure in wide use in which the status of selected components is determined in response to control signals from the host processing unit. Trace signals are signals from a multiplicity of selected locations in the target processor 12 during defined period of operation. While the width of the bus 15 interfacing to the host processing unit 10 generally has a standardized dimension, the bus between the emulation unit 11 and the target processor 12 can be increased to accommodate an increasing amount of data needed to verify the operation of the target processing unit 12. Part of the interface function between the host processing unit 10 and the target processor 12 is to store the test signals until the signals can be transmitted to the host processing unit 10.
In the prior art, the trace streams carry test and debug data from the target processor to the host processing unit in signal groups, the signal groups including signal packets. The trace packets are groups of data, a plurality of packets typically being transmitted together. The packets can be relatively small, e.g., each packet has an 8 bit payload (information signal group) in the preferred embodiment. The small size of the packets permits great flexibility in transmission through non-standardized interfaces. One of the trace streams is typically a timing trace stream. Each timing packet group typically includes a header packet and a plurality of information packets. The timing data identifies an activity or a non-activity of the program counter during each clock cycle. Therefore, a logic signal must be transmitted for each clock cycle of the target processing unit in order to reconstruct the activity of the target processor. Moreover, an appreciable part of the bandwidth of the trace streams can be used in transmission of the timing data. Because of the large amount of data that must be transmitted from the increasingly complex target processors to host processing unit for analysis, minimizing the transmission of data is important.
A need has been felt for apparatus and an associated method having the feature of reducing the amount of information that must be transmitted by the trace stream to the host processing unit. It would be another feature of the apparatus and associated method to reduce the amount of information used to represent the timing parameters of target processing unit. It would be yet another feature of the apparatus and associated method to provide flexibility in transmitting data in timing packet groups. It would a still another feature of the apparatus and associated method to provide timing packet groups capable of compressing the timing information of the target processor. It is a more particular feature of the apparatus and associated method to replace a timing packet group in which each data bit position represents the same logic signal with a smaller timing packet group.